Full beginner lecture
Assembly Tracing
Intuition
Assembly tracing은 CPU가 된 것처럼 한 instruction씩 state를 바꾸는 연습입니다. state는 보통 PC, relevant registers, relevant memory입니다. 좋은 trace는 모든 register를 다시 쓰지 않습니다. 바뀐 register, 바뀐 memory, next PC만 정확히 표시합니다.
Rule
각 step은 같은 순서로 처리합니다. current PC의 instruction을 고릅니다. source register와 immediate를 old state에서 읽습니다. ALU result, effective address, branch condition을 계산합니다. register writeback 또는 memory write를 적용합니다. 마지막에 next PC를 정합니다.
일반 RV32I instruction은 4 byte이므로 next PC는 보통 PC+4입니다. taken branch와 jump는 target으로 갑니다. x0는 write해도 0입니다. lw는 memory에서 register로, sw는 register에서 memory로 값이 이동합니다.
Visual Block
One-step trace board
PC instruction read values calculation writeback next PC
0x100 addi t0,zero,3 zero=0 imm=3 0+3=3 t0=3 0x104
0x104 sw t0,8(sp) t0=3 sp=0x8000 EA=0x8008 mem[0x8008]=3 0x108
Memory direction for load and store
lw t1, 8(sp): memory[sp+8] -> t1
sw t1, 8(sp): t1 -> memory[sp+8]
Worked Example 1
Initial state. PC=0x100, zero=0, t1=7, t2=5.
0x100: addi t0, zero, 3
0x104: add t3, t0, t1
0x108: addi t2, t2, -2
- At
0x100, 0+3=3, so t0=3, next PC=0x104. - At
0x104, read current t0=3 and t1=7, so t3=10, next PC=0x108. - At
0x108, read old t2=5, so t2=3, next PC=0x10C.
Final changed registers are t0=3, t3=10, t2=3.
Worked Example 2
Initial state. PC=0x200, sp=0x8000, t0=13, memory[0x8008]=99.
0x200: sw t0, 8(sp)
0x204: lw t1, 8(sp)
0x208: addi t1, t1, 1
sw computes EA=0x8000+8=0x8008 and stores t0=13. Memory becomes memory[0x8008]=13.lw reads the current memory value 13 and writes t1=13.addi reads old t1=13, writes t1=14.
Final state is memory[0x8008]=13, t1=14, PC=0x20C.
Common Mistakes
- Advancing PC before executing the current instruction.
- Treating
sw like lw and changing the register instead of memory. - Using initial memory after a previous store already changed it.
- Executing a skipped instruction after a taken branch.
Active Recall
- What is the first value to inspect in a trace step.
- In
addi t0,t0,1, do you read old t0 or new t0. - For
beq t0,t1,L, what happens when the values differ. - What changes after
sw t1,0(sp).
Source Grounding
Uebung 2 and Uebung 2 Musterloesung: hand execution, immediates, Ripes.Vorlesung Teil 1: RISC-V ISA and machine execution model.tutor_spec.md: trace mode expects PC, changed registers, relevant memory, and active instruction.